1. Field of the Invention
The present invention relates to a semiconductor storage device that is preferably used as synchronous DRAM (Dynamic Random Access Memory).
Priority is claimed on Japanese Patent Application No. 2007-300931, filed Nov. 20, 2007, the content of which is incorporated herein by reference.
2. Description of the Related Art
A memory array (also referred to as a memory cell array) in a semiconductor storage device includes sense amps that amplify data from each of memory cells, sub-word drivers that drive a word line, and a memory mat (hereinafter, “MAT”) that includes multiple memory cells and is surrounded by an array of the sense amps and the sub-word drivers.
A local IO line (Input-Output line) (hereinafter, “LIO”) that connects sense amps forming a sense amp sequence between the memory mats to one another, and a main IO line (hereinafter, “MIO”) crossing LIO and shared by all of the memory mats are arranged in the memory array. An amplifier (called a read/write amp or a sub-amp, hereinafter called a “read/write amp”) that amplifies data is arranged at an LIO-and-MIO intersection region (see FIG. 1). In DDR2 SDRAM (Double Data Rate 2 Synchronous Dynamic Random Access Memory), four inputs and outputs of data are simultaneously executed through LIO and MIO with respect to 1 DQ (1 data signal) to support a 4-bit prefetch.
FIG. 1 is a schematic plane view showing the arrangement of read/write amps in the memory array. An 8M-bit memory space in the case of 512M-bit DDR2 is shown. Sense amp regions SAs each including multiple sense amps, LIOs connected to the sense amps, sub-word driver regions SWDs each including a sub-word driver having the configuration in which a driver of a word line is divided, MIOs that are shared by all of the memory mats are arranged among MATs. Since four inputs and outputs are required for 1 DQ to support a 4-bit prefetch, four MIOs are simultaneously used in the configuration shown in FIG. 1. One read/write amp (hereinafter, “RWA”) is arranged at each intersection region of two LIOs with two MIOs in the case of FIG. 1.
In the configuration, four RWAs surrounding one MAT to be accessed are activated upon the reading and writing of 1 DQ data.
When 2 DQ (2 data signals) are allocated to the same memory region as that in an original product such as DDR SDRAM utilizing 2-bit prefetch to reduce memory capacity or implement multiple I/O (input/output), the number of MIOs become double, and two RWAs need to be arranged at the MIO-and LIO intersection region. However, regions among MATs widen when two RWAs are arranged at each intersection region, and thereby, the entire area of the memory array increases.
Japanese Unexamined Patent Applications, First Publication Nos. 2003-223785, H05-234377, 2006-172577, and 2003-346479 are prior arts concerning control of memory mats, banks, and plates that are formed by compartmentalizing the memory array.
However, none of the prior arts can solve the problem of the area increase when two RWAs are arranged at each MIO-and-LIO intersection region.